1. Field of the Invention
The invention relates in general to a level shifter circuit, and more particularly to a level shifter circuit capable of increasing a shifting-speed and decreasing a short current.
2. Description of the Related Art
FIG. 1 (Prior Art) is a circuit diagram showing a conventional level shifter circuit 10. Referring to FIG. 1, the conventional level shifter circuit 10 includes a level shifter 110 and an inverter 120. The inverter 120 receives an input signal IN and inverts the input signal IN into an inversion input signal IN′ to be outputted to the level shifter 110. The inverter 120 includes a transistor P3 and a transistor N3, which are respectively a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxidation semiconductor (NMOS) transistor. The control terminal of the transistor P3 is coupled to the control terminals of the transistor N3 and a transistor N1, and the second terminal of the transistor P3 is coupled to the first terminal of the transistor N3 and the control terminal of a transistor N2. The first terminal of the transistor P3 and the second terminal of the transistor N3 respectively receive a power voltage Vcc and a power voltage Vss.
The level shifter 110 outputs an output signal OUT and an inversion output signal OUT′ ranging from VDD to Vss according to the levels of the input signal IN and the inversion input signal IN′. The input signal IN and the inversion input signal IN′ may range from 0 to 1.8V, while VDD and Vss are respectively 5V and 0V, for example.
The level shifter 110 further includes the transistor N1, a transistor P1, the transistor N2 and a transistor P2, wherein the transistor N1 and the transistor N2 are NMOS transistors, while the transistor P1 and the transistor P2 are PMOS transistors, for example. The transistor N1 and the transistor P1 are respectively controlled by the input signal IN and the output signal OUT to output the inversion output signal OUT′, while the transistor N2 and the transistor P2 are respectively controlled by the inversion input signal IN′ and the inversion output signal OUT′ to output the output signal OUT.
The first terminals of the transistor P1 and the transistor P2 are coupled to a power voltage VDD. The second terminal of the transistor P1 is coupled to the first terminal of the transistor N1 and the control terminal of the transistor P2. The second terminal of the transistor P2 is coupled to the first terminal of the transistor N2 and the control terminal of the transistor P1. The second terminals of the transistor N1 and the transistor N2 receive the power voltage Vss. The control terminals of the transistor N1 and the transistor N2 respectively receive the input signal IN and the inversion input signal IN′.
FIG. 2 (Prior Art) shows waveforms of the input signal, the inversion input signal, the output signal and the inversion output signal of the conventional level shifter circuit. As shown in FIG. 2, the input signal IN, the inversion input signal IN′, the output signal OUT and the inversion output signal OUT′ are respectively represented by curves 210, 220, 230 and 240. When the input signal IN is changed from 0V to 1.8V, the output signal OUT is changed from 0V to 5V. That is, the conventional level shifter circuit 10 converts the low voltage level of 1.8V into the high voltage level of 5V for output. The inversion input signal IN′ is changed from 1.8V to 0V, and the inversion output signal OUT′ is changed from 5V to 0V
FIG. 3 (Prior Art) shows a waveform of a short current of the conventional level shifter circuit. As shown in FIG. 3, the short current of the conventional level shifter circuit 10 is represented by the curve 310. As can be clearly understood from the curve 310, a short current IDS1 generated by the conventional level shifter circuit 10 approaches 30 uA at the time of 4 n seconds.
In the conventional level shifter circuit 10 (see FIG. 1), however, when the transistor N1 is turned on, the short current IDS1 flows through the transistor N1 and the transistor P1 because the transistor P1 is not turned off in time. In addition, because the transistor N1 and the transistor P1 are in the on state, the inversion output signal OUT′ has the fighting phenomenon between the power voltage VDD and the power voltage Vss.
According to the same working principle, when the transistor N2 is turned on, another short current IDS1 often flows through the transistor N2 and the transistor P2 because the transistor P2 is not turned off. In addition, because the transistor N2 and the transistor P2 are in the on state, the output signal OUT has the fighting phenomenon between the power voltage VDD and the power voltage Vss.
Consequently, the conventional level shifter circuit 10 becomes too slow, and the short current IDS1 also causes the unessential power consumption of the level shifter circuit 10. In addition, when the power voltage Vcc is powered down and the power voltage VDD is still powered on, the higher leakage current is induced because the output signal OUT and the inversion output signal OUT′ are floating.